Senior Physical Design Engineer (Floorplan & PnR)

Job Overview

Envision Employment Solutions is seeking a Senior Physical Design Engineer specializing in Floorplanning and Place & Route (PnR) for a leading IT Services and IT Consulting partner. This role focuses on the physical implementation of complex digital designs, driving timing closure, power optimization, and design sign-off for advanced technology nodes.

Key Responsibilities

• Develop and optimize floorplans for high-performance, low-power SoC designs including macro placement, IO planning, and power grid architecture.
• Execute full-chip Place & Route (PnR) flow from netlist to GDSII, including placement, clock tree synthesis (CTS), routing, and post-route optimization.
• Drive timing closure across multiple corners and modes using STA tools; resolve setup/hold violations, max transition, and capacitance issues.
• Perform power analysis and optimization (dynamic and leakage) using UPF/CPF low-power methodologies.
• Run physical verification (DRC/LVS/ERC/antenna) and coordinate sign-off closure with foundry rules.
• Conduct IR drop and electromigration analysis; implement mitigation strategies for power integrity.
• Collaborate with front-end design, DFT, and verification teams to ensure design convergence and manufacturability.
• Develop and maintain automation scripts (Tcl, Python, Perl) to enhance PnR flow efficiency and methodology.
• Evaluate and adopt new EDA tool features and methodologies for advanced nodes (7nm, 5nm, 3nm).

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Senior-level experience in physical design implementation for complex digital ICs.
• Deep expertise in floorplanning, placement, CTS, routing, and timing closure flows.
• Proficiency with industry-standard EDA tools: Cadence Innovus/GeniUS, Synopsys ICC2/Fusion Compiler, PrimeTime, Voltus, and Calibre.
• Strong scripting skills in Tcl, Python, or Perl for flow automation and customization.
• Solid understanding of low-power design techniques (UPF/CPF), multi-voltage domains, and power gating.
• Experience with advanced process nodes (FinFET) and foundry-specific design rules.
• Excellent problem-solving abilities and cross-functional communication skills.

Preferred Skills

• Knowledge of hierarchical and multi-die/3D-IC physical design methodologies.
• Experience with machine learning applications in PnR (e.g., predictive timing, congestion modeling).
• Familiarity with DFT integration (scan chain, ATPG) at physical level.
• Prior exposure to automotive (ISO 26262) or safety-critical design flows.