Lead STA Engineer - Static Timing Analysis Lead - Cairo Egypt

About the Role

Envision Employment Solutions is partnering with a leading IT Services and IT Consulting company to recruit a Lead STA Engineer for their Cairo, Egypt operations. This senior-level position focuses on Static Timing Analysis (STA) signoff for advanced semiconductor designs. The successful candidate will own timing closure methodology, drive signoff quality, and mentor a team of STA engineers across complex SoC and IP projects targeting advanced process nodes.

Key Responsibilities

• Lead full-chip STA signoff flow including setup, hold, and pulse-width checks across all PVT corners and operating modes
• Define and maintain timing signoff methodology for advanced technology nodes (7nm, 5nm, 3nm) using industry-standard tools (PrimeTime, Tempus, or equivalent)
• Drive timing closure from RTL through GDSII, collaborating with RTL design, synthesis, physical design, and DFT teams
• Develop and validate timing constraints (SDC), exception handling, and clock-gating verification strategies
• Perform on-chip variation (OCV), advanced OCV (AOCV), and parametric OCV (POCV) analysis for signoff accuracy
• Own IR-drop aware timing analysis, EM-IR signoff coordination, and voltage-aware STA flows
• Mentor and guide junior STA engineers; conduct design reviews and methodology training sessions
• Automate STA flows using Python, Tcl, Perl scripting for regression efficiency and metric tracking
• Collaborate with foundry and EDA vendors on library characterization, liberty validation, and new feature enablement
• Prepare and present timing signoff reports for tape-out readiness reviews and customer deliverables

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Microelectronics
• 8+ years of hands-on experience in Static Timing Analysis for ASIC/SoC designs
• Proven track record of multiple successful tape-outs at 28nm and below (FinFET experience mandatory)
• Expert proficiency with Synopsys PrimeTime or Cadence Tempus signoff flows
• Deep understanding of SDC constraint development, clock domain crossing (CDC), and multi-mode multi-corner (MMMC) analysis
• Strong experience with hierarchical STA, block-level abstraction, and bottom-up/top-down flows
• Solid knowledge of signal integrity (SI), crosstalk, and noise-aware timing analysis
• Familiarity with low-power design techniques (UPF/CPF), power gating, multi-Vt, and DVFS timing verification
• Excellent scripting skills in Python, Tcl, or Perl for flow automation and custom checks
• Strong communication skills in English; ability to work cross-functionally in a global team environment

Preferred Skills

• Experience with machine learning-based timing prediction or AI-driven closure techniques
• Knowledge of 3D-IC, chiplet, or advanced packaging timing challenges
• Prior experience in automotive (ISO 26262) or safety-critical STA flows
• Contributions to EDA tool methodology development or open-source STA automation projects
• Familiarity with formal verification and equivalence checking (Lec, Conformal) for timing signoff support